The present invention relates to a static, pass-transistor, logic family and, more particularly, to a Forecasted-Restoration Complementary Pass-Gate (FRCPG) logic family. The advantages of the new FRCPG logic family are speed improvement and lower energy dissipation than in the prior art static pass transistor logic families.
General Description:
Pass-transistor logic, in the present discussion, consists of a type of metal/oxide-or-insulator/silicon-or-semiconductor (MOS) logic integrated in integrated circuits (IC's). MOS transistors are used as switches. An n-channel (NMOS or nmos) transistor is turned on by application of a positive input voltage, approximately equal to the positive supply voltage, to the nmos gate terminal, and is preferably turned off by connecting the nmos gate to a voltage approximately the value of the negative supply terminal voltage. A p-channel (PMOS or pmos) device is turned on by connecting the pmos gate to a voltage approximately the value of the negative supply, while the pmos is preferably turned off by connecting the pmos gate to a voltage approximately the value of the positive supply voltage.
The problem with pass-transistor logic is that the pass-transistors, which function in a sense, ideally, as series switches in a logic-signal, signal path, for the logic input which connects to a source/drain diffusion, also function as source followers with respect to the gate input of the pass-transistor. Thus, for a simple pass-transistor gate, an nmos drain will be one input terminal, the nmos gate will be a second input terminal, and the nmos source will be the output terminal. Now, if both the drain voltage is high and the gate voltage is high, then the output, source voltage will be high. High means approximately equal to the positive logic-level voltage, usually the positive supply voltage. But for each such AND gate which a logic signal is required to propagate, by way of a series of gate-input-connections, the logic gate output voltage will be one nmos-transistors gate-source threshold voltage lower than the nmos-gate-terminal logic gate input voltage. Similarly, a pmos AND gate would suffer from an upward level-shifting of the output voltage with respect to the pmos-gate terminal input voltage.
Thus, it is necessary after each pass-transistor logic gate, or after each so-many logic gates, to perform a logic-level "restoration". The need for restoration is due to the fact that the "weak logic state 1", a logical 1 having a dc level one threshold voltage below the positve rail, will cause DC voltage leakage if the weak logic state 1 output will then be used as an input to another, following, cmos gate, since the input PMOS of a cmos gate will then not be completely turned off. In addition if the weak logic state 1 will be used as a gate signal to another NMOS pass transistor, the NMOS pass transistor output will then be two threshold-voltage drops lower than the positive rail. This is the problem discussed in the previous paragraph with respect to AND gate use of the pass transistors. In complementary MOS (CMOS or cmos) logic, the output of the basic pass-transistor logic gate is connected to a cmos inverter input. The cmos inverter output swing is from supply-rail to supply-rail. Therefore, the logic level of the inverter output logic signal has been restored to the ideal logic-level values. The restoration is due to the PMOS latch before the output inverter that is used only as a buffer. This latch is not always used in CPL, which is discussed below. The "original" CPL, to be discussed below does not have this PMOS latch and hence suffers from leakage at the inverter, due to the reason mentioned in reference 4. The inversion due to the cmos inverter must be taken into account in the system logic design. The easiest way to accommodate the additional logic-signal logical inversion due to the added inverter, is to include the inverter in the unit pass-gate design, with the resulting pass-transistor logic gate then including both the correct logic function terminal definition, and including logic level restoration. The FRCPG logic family of the present invention incorporates these features.
The new, inventive, "forecasting" feature of the present invention of the need for signal-level restoration in the logic gate, is based on Applicant's realization that the need for output signal logic-level restoration in AND/NAND an OR/NOR gates can be predicted according to a single logic-gate input.
Prior Art & Problems:
Static pass-transistor logic families are used extensively in large custom arrays, such as multipliers and adders. The two main reasons for using static pass-transistor logic is the higher logic-gate functionality per transistor count in a given delay time, and the lower overall capacitance than obtained with conventional logic families, such as CMOS logic, for example. This typically results in lower power consumption and higher operation speed, yielding a lower power-delay product, which usually gives an indication about the lower circuit energy dissipation.
There are several different approaches to implement static pass logic gates. These can be divided into two main categories. In the first category, only one pass-transistor type is used, usually n-channel, combined with output signal restoration, in order to achieve full rail-to-rail swing. In the second category, both n-channel and p-channel pass transistors are used, and signal restoration is not needed, for example, double-pass logic (DPL), or conventional full-CMOS transmission gates, which employ parallel p-channel and n-channel switches. In general, the second category uses more transistors, and thus presents higher input capacitance, but at the same time provides shorter delay times in some applications.
Energy consumption is especially important in battery-operated systems, as battery life is defined in terms of energy, rather than simply power. For a given architecture, ic manufacturing process, supply voltage, and operating frequency, the energy waste is mainly due to the circuit's parasitic capacitance and the feed-through (short-circuit) currents.
When using pass logic families, the overall capacitance is usually reduced compared with conventional CMOS implementations.
The present invention presents a way to reduce the feed through currents in static pass logic families with signal restoration. This is accomplished by using output signal restoration only when the restoration is needed, and to eliminate the restoration when the restoration conflicts the inputs--i.e., results in a logic state in which both the logic input pass transistor and the restoration-logic transistor are conducting simultaneously, resulting in increased current drain from the power supply, and, hence, increased power dissipation. The implementation is based on the fact that in both the AND and NOR gates, it is sufficient to observe only one input in order to predict the chances of the output being high. By using this conditional restoration method, the overall energy consumption is reduced.
Prior-art pass logic families with output restoration are shown in FIGS. 1A-1D. These prior art logic families are
(A) complementary pass logic (CPL),
(B) swing restoration pass logic (SRPL),
(C) energy economized pass logic (EEPL), and
(D) push pull pass logic (PPPL).
Comparison of the different pass logic families follows.
Both the CPL, FIG. 1A, and PPPL, FIG. 1D, gates can operate properly also without the buffering inverters at the output. In some circuit applications, CPL and PPPL may be used without output level performance degradation, but the number of series connected pass transistors is still limited by the distributed R-C. This has the effect of energy reduction, since overall less capacitance must be charged and discharged. SRPL, FIG. 1B, and EEPL, FIG. 1C, on the other hand, must employ buffers as part of their restoration scheme.
The PPPL drive capability, without output buffers, can be better than the drive capability of CPL. but only WHEN Q=1, where the n-channel, N5, FIG. 1D, restoration transistor is on. The fact that PPPL uses p-channel pass transistors increases the logic gate input capacitance, due to the larger size needed for the p-channel devices than for the n-channel devices. In addition, since both p-channel and n-channel restoration transistors are used, the feed-through current is larger when point Q is changed from "1" to "0", since both restoration transistors, N5 and P5, are on at the beginning of the phase. When observing both points Q and Q', where Q' indicates "Q-bar", PPPL has six logic states with conflict currents between input and restoration. (AB=00, 01, 10, both for Q and Q'), while CPL has only four logic states with conflict currents between input and restoration. (AB=00, 01, 10, for Q; and AB-11 for Q').
SRPL, FIG. 1B, requires using larger n-channel pass transistors, implying larger logic-gate input capacitance compared with CPL, in order to turn over the latch at the SRPL logic-gate output. This problem becomes worse when many gates are cascaded, and the SRPL can even fail to switch to ground.
For both SRPL and EEPL, there is always a conflict between the restoration current and the inputs when the outputs are changed, since restoration is done from the complementary output.
In EEPL, restoration is done only after a delay introduced by the output inverters, which makes EEPL slower than CPL, but EEPL has the advantage of reduced peak power consumption. However, the average power consumption of EEPL is practically the same as the average power consumption of CPL.
In general, the restoration scheme introduces a power waste, combined with an increase in the delay time, due to the feed-through current flowing from the restoration transistor to the input pass transistor. This problem is addressed in the novel forecast-restoration circuits of the present invention.
The static pass-transistor logic families of the circuits of FIGS. 1A-1D represent the attempts to optimize speed and power consumption in the face of the need for output signal-level restoration. Each of the prior art circuits has disadvantages, as discussed above.
There is thus a widely recognized need for, and it would be highly advantageous to have, an output signal-level restoration scheme that provides improved speed with lower power consumption, while providing the required output signal-level restoration.